The subject matter disclosed herein relates to solutions for utilizing inverse reactive ion etching (RIE) lag in double patterning contact formation. More specifically, the subject matter disclosed herein relates to forming a semiconductor device using a contact double patterning process with variable etch rates.
Fabricating highly integrated semiconductor devices involves using highly miniaturized patterns. As semiconductor devices have reduced in size, individual elements within the devices have become smaller. Particularly, as semiconductor fabrication has moved from the 45 nanometer process to the 32 nanometer process and below, double patterning techniques have been used in order to provide minimum pitch and critical dimensions through lithography processes. However, double patterning alone has not allowed for the controlled fabrication of contacts in certain semiconductor devices.